Search - Design Compiler

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Description: 编译原理课程设计词法分析好东西多多支持哦-Principles of curriculum design compiler lexical analysis can support a good thing Oh
Platform: | Size: 2048 | Author: ouyangchangqi | Hits:

[ELanguage] Simple

Description: 编译原理实验：设计并实现一个Simple语言的编译器-Compiler Principle Experiment: Design and realization of a Simple Language compiler
Platform: | Size: 707584 | Author: 陈飞 | Hits:

[Linux-Unix] cla_dc

Description: a demo script of "carry lookahead adder" for synopsys design compiler
Platform: | Size: 2048 | Author: heyong | Hits:

Description: 编译原理课程设计，LL(1)方法，用FIRST（）和FOLLOW（），SELECT（），以及预测分析表-Principles of curriculum design compiler, LL (1) method, FIRST () and FOLLOW (), SELECT (), as well as predictive analysis table
Platform: | Size: 3383296 | Author: ZOU | Hits:

[ELanguage] cffxq

Description: 编译器设计的编译程序涉及到编译五个阶段中的三个，即词法分析器、语法分析器和中间代码生成器。编译程序的输出结果包括词法分析后的二元式序列、变量名表、状态栈分析过程显示及四元式序列程序。整个编译程序分为三部分：词法分析部分、语法分析处理及四元式生成部分、输出显示部分。-Compiler design compiler compiler involved in three of five stages, namely, lexical analyzer, syntax analyzer and intermediate code generator. Compiler output results include lexical analysis of binary sequence, variable watch, state stack analysis shows and quaternion sequence procedures. The entire compiler is divided into three parts: part of lexical analysis, grammar analysis and to generate part of quaternion type, the output display.
Platform: | Size: 177152 | Author: 佚星 | Hits:

[SCM] DHRY

Description: The DHRY program performs the dhrystone benchmarks on the 8051. Dhrystone is a general-performance benchmark test originally developed by Reinhold Weicker in 1984. This benchmark is used to measure and compare the performance of different computers or, in this case, the efficiency of the code generated for the same computer by different compilers. The test reports general performance in dhrystones per second. Like most benchmark programs, dhrystone consists of standard code and concentrates on string handling. It uses no floating-point operations. It is heavily influenced by hardware and software design, compiler and linker options, code optimizing, cache memory, wait states, and integer data types. The DHRY program is available in different targets: Simulator: Large Model: DHRY example in LARGE model for Simulation Philips 80C51MX: DHRY example in LARGE model for the Philips 80C51MC
Platform: | Size: 23552 | Author: aglo | Hits:

[ELanguage] kecengsheji

Description: 编译原理课程设计，做了一个：根据LR分析表构造LR分析器！对同学们做编译原理实验很有帮助-Principles of curriculum design compiler, made a: LR analysis table constructed in accordance with LR parser! For students to do experimental helpful Compilation Principle
Platform: | Size: 264192 | Author: lyf | Hits:

[Other] modern.Compiler.Design

Description: 集中讲述所有语言范型通用的传统技术和高级技术,使读者具备现代编译程序构造所需的技能.涵盖了所有主要的程序设计语言类型-命令式,面向对象,函数式,逻辑式和分布式语言.通过大量实例进行说明,直观易懂.-Focus on all languages commonly used paradigm of traditional technologies and advanced technology, so that readers construct a modern compiler the necessary skills. Covers all major types of programming languages- imperative, object-oriented, functional, logic and the distribution of language. through a large number of examples show that intuitive easy to understand.
Platform: | Size: 15144960 | Author: zhengks | Hits:

[VHDL-FPGA-Verilog] ebook_verilog_fine_state_machine

Description: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
Platform: | Size: 121856 | Author: rex | Hits:

[ELanguage] Compiler

Description: 本设计Tiger语言为源语言，制作了编译程序的前端部分，主要包括了词法分析、语法分析、抽象语法树和类型检查的设计和实现方法，以及课程设计中碰到的问题、实验心得、参考数据等。-Tiger of the design language for the source language, has produced a compiler front-end parts, including the lexical analysis, syntax analysis, abstract syntax tree and the type checking of the design and implementation, as well as curriculum design problems they encountered in the experimental experience, reference data.
Platform: | Size: 390144 | Author: jack sio | Hits:

[Other] Compiler

Description: 正规文法到正规式的算法实现编译原理课程设计-Of grammar-based algorithm to the formal principles of curriculum design to achieve the compiler
Platform: | Size: 629760 | Author: 刘玮 | Hits:

[ELanguage] pascal-compiler-in-cpp

Description: pascal compiler in C++是一个用C++实现的PASCAL编译器，主要包括符号表，创建语法树，代码生成和4元式解析等。该工程是根据龙书实现的编译器。项目中大量使用了STL，设计模式等思想。是学习面向对象编程和设计的好材料。里面包含有说明.txt有更详细说明请使用Mingw或Dev-C++开发环境-pascal compiler in C++ is a compiler which compiles pascal code. The project consists of Symbol Table, Abstract Tree Construction, Code generation and generated code interpretation. I believe it s a helpful material for learning oo programming and design since it uses STL and design patterns intensively. The project is developed on Mingw and Dev-C++ IDE, VC6.0 is not supported since it does not STL compliant!
Platform: | Size: 721920 | Author: xukeying | Hits:

[VHDL-FPGA-Verilog] ASIC_Design_Flow_Tutorial_with_synopsys

Description: Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
Platform: | Size: 4128768 | Author: Kang | Hits:

[Linux-Unix] compiler

Description: compiler design in C source
Platform: | Size: 492544 | Author: syhsu | Hits:

[VHDL-FPGA-Verilog] 4Day

Description: 《4天学会Design Compiler》的中文版。《4天学会Design Compiler》大家都该知道的，一个很好的DC入门教才，我也是学习时找到了这个中文版。《4天学会Design Compiler》可以在xunlei上下载到。-" 4-day Institute of Design Compiler" the Chinese version. " 4-day Institute of Design Compiler" Everyone in the know, a good DC to teach entry-only, I also found this when studying Chinese. " 4-day Institute of Design Compiler" can be downloaded to xunlei.
Platform: | Size: 605184 | Author: 唐霖 | Hits:

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[Other resource] token

[ELanguage] Simple

[Linux-Unix] cla_dc

[ELanguage] LL1ForWin

[ELanguage] cffxq

[SCM] DHRY

[ELanguage] kecengsheji

[Other] modern.Compiler.Design

[VHDL-FPGA-Verilog] ebook_verilog_fine_state_machine

[ELanguage] Compiler

[Other] Compiler

[ELanguage] pascal-compiler-in-cpp

[VHDL-FPGA-Verilog] ASIC_Design_Flow_Tutorial_with_synopsys

[Linux-Unix] compiler

[VHDL-FPGA-Verilog] 4Day

[Crack Hack] RTL-to-Gates-Synthesis-using-Synopsys-Design-Comp

[ELanguage] c-compiler-design-source

[ELanguage] compiler-hw

[ELanguage] compiler-theory-PL0

[Software Engineering] EOCC---Scanner-Design

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